The methods used to manufacture integrated circuits very often introduce defects. Thus, after manufacture, each integrated circuit is subjected to tests aimed at detecting the presence of such defects. In the case of non-volatile memories, it is ascertained first of all that the column and row decoders of the memory are working properly by programming cells of the memory array in predetermined configurations, and then carrying out successive readings of these same cells. Any divergence between the data elements that should have been written and the data elements read indicates the presence of a defect.
The leakage current of these memory cells is then measured, and, thus, it is ascertained that the value of this leakage current is acceptable or not acceptable. The source of these leakage currents is varied: it may be the presence of electrical charges in the oxide layer of the transistor of the memory cell or a defect in the structure of the memory cell that, for example, generates a leakage current.
At the present time, this measurement of leakage current is an analog measurement done by means of a testing apparatus whose inputs are connected to the external terminals of the memory to be tested. In practice, a cell to be tested is selected by the application to its grid of a zero voltage, and the current flowing in the bit line connected to this cell is measured. The leakage current is then accessible on the data pad associated with the cell, care being taken to short-circuit the read circuit connected to the bit line concerned. The value of the leakage current measured is then compared with a current threshold value indicating whether the cell is defective or not. Typically, the maximum leakage current acceptable for a cell is in the range of 10 microamperes for a reference current in the range of 50 to 100 microamperes. The testing apparatus is generally a programmed unit designed to generate the addresses of the memory cells of the matrix one-by-one, and measure the leakage current flowing in the corresponding bit line for each of the memory cells.
The main drawback of this measurement of the leakage current lies in its relatively lengthy performance time, for it is an analog measurement. The use of equipment external to the memory is another drawback for it is liable to introduce unwanted currents, and, hence, falsify the measurement of the leakage current.
One approach to address these drawbacks includes using the read circuit of the memory to perform this measurement. Usually, the read circuit of a non-volatile memory is entrusted with the task of comparing the current flowing through a memory cell with a reference current during a reading phase. During the reading phase a read voltage is applied to the grid of the memory cell to be read. The read circuit then delivers a logic data element indicating whether the current of the cell is smaller than or greater than the reference current which, for its part, is set by a reference cell.
To measure the leakage current of a memory cell, it would be enough to apply a zero voltage to the grid of the memory cell to be tested and then compare the leakage current with a reference current equal to a predetermined maximum leakage current. However, this technique, which could very easily be implemented in standard memories, is not very precise. Indeed, when the reference current is very low, in the range of some microamperes, the low value of the reference current can no longer be used for the accurate biasing of the current mirror of the read circuit, since the gate-source voltage of the transistors of the current mirror tends to approach the conduction threshold Vt of the transistors. The duplication of the current by the current mirror becomes imprecise and the read circuit is very sensitive to noise.